1. Field of the Invention
This invention relates to a display control apparatus and a display control method, which displays an image on each of a plurality of display devices.
2. Description of the Related Art
FIG. 9 is a schematic block diagram of one example of a related display control apparatus. In the past, in order to display an independent image on each of a plurality of display monitors (display monitors a 400, b 500), a display control apparatus 100 is equipped with display units (display units a 260, b 270) of the same number of the display monitors, and took such a configuration that each display unit is directly connected to an internal bus 230 (e.g., see LCD/CRT 2D Graphic Subsystem Data Book, Version 0.08, May 26, 2000 (nVIDIA Corporation)).
The display control apparatus 100, which is shown in FIG. 9, is equipped with a memory interface 240, a display unit a 260, a display unit b 270 and other internal blocks 220, which were connected by the internal bus 230.
The display unit a 260 is connected to a display monitor a 400, and has, in an inside of the display unit a 260, a synchronizing signal generating section 261, a bus access control section 262, a screen combining section 263, a buffer control section 265, a buffer section 266 and a display IF section 264. The display unit b 270 is connected to a display monitor b 500, and is of a similar configuration to the display unit a 260. The memory interface 240 is directly connected to a local memory 300 which is provided outside an display control apparatus 100, and arbitrates use request signals of the internal bus 230, from the display unit a 260, the display unit b 270, and other internal blocks 220, and issues a use permission signal of the internal bus 230 to any one of them.
The synchronizing signal generating section 261, which is provided in an inside of the display unit a 260, generates a display synchronizing signal which corresponds to an image that the display monitor a 400 displays. The bus access control section 262 outputs a use request signal of the internal bus 230, to the memory interface 240, at timing of the synchronizing signal, in accordance with an image display parameter which is set up by a register etc. The bus access control section 262 receives an internal bus use permission signal from the memory interface 240, and then, reads out video data which is stored on the local memory 300, through the internal bus 230, and outputs the video data to the screen combining section 263.
The screen combining section 263 applies screen combining processing to video data which is inputted from the bus access control section 262 and video data which is read out from the buffer section 266 through the buffer control section 265, in accordance with a screen combining parameter which is given by register setup etc., and stores video data, which was processed to be combined, in the buffer section 266 through the buffer control section 265. The display IF section 264 reads out video data which is stored in the buffer section 266, through the buffer control section 265, in accordance with timing of the synchronizing signal, and outputs the video data and the synchronizing signal to the display monitor a 400.
In addition, the buffer section 266 is configured by two buffers, and one buffer is connected to the screen combining section 263 through the buffer control section 265, and carries out an input of video data from the screen combining section 263 and an output of video data to the screen combining section 263, and the other buffer is connected to the display IF section 264 through the buffer control section 265, and outputs video data to the display IF section 264.
The buffer control section 265 switches a connection relation of the buffer section 266 and the screen combining section 263 and the display IF section 264 every certain fixed cycle (e.g., one cycle of the synchronizing signal), and carries out such double buffering processing that it outputs video data to the display IF section 264, from a buffer which has stored video data outputted from the screen combining section 263 in an immediately preceding cycle, and stores video data which was outputted from the screen combining section 263, in a buffer which outputted video data to the display IF section 264 in an immediately preceding cycle, at the same time, and outputs this to the display IF section 264 in an immediately following cycle. The buffer control section 265 outputs video data which is displayed on the display monitor a 400, to the display IF section 264, without a break, by the double buffering processing.
The display unit b 270 carries out similar processing to that of the display unit a 260, and outputs video data to the display monitor b 500. In addition, the display monitor a 400 and the display monitor b 500 display video data which was output from the display unit a 260 and the display unit b 270 respectively, on screens.
However, in the related display control apparatus, in order to display images on a plurality of display devices, there is a necessity to have a plurality of display units, and there is such circumstances that a circuit size gets larger, and cost increases.